Serdar Sayın (ssayin)

ssayin

Geek Repo

Location:Ankara, Turkey

Home Page:serdarsayin.com

Github PK Tool:Github PK Tool

Serdar Sayın's repositories

riscv32-cosim-model

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

Language:SystemVerilogLicense:Apache-2.0Stargazers:5Issues:1Issues:0

riscv32-sim

An easy-to-use, still-in-development RISC-V 32-bit instruction-accurate (IA) simulator.

Language:C++License:MITStargazers:1Issues:1Issues:0

aragor-s-celestial-quest

LaTeX source files for my book "Aragor's Celestial Quest."

Language:TeXStargazers:0Issues:0Issues:0

branch-coverage

BIL481 Assignment 2

Language:JavaStargazers:0Issues:0Issues:0

circt

Circuit IR Compilers and Tools

Language:C++License:NOASSERTIONStargazers:0Issues:0Issues:0

city

2016-2017 Spring BIL 214 Homework 3

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language:HaskellLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

dumb-jose

Insecure library for an insecure format. GitHub mirror from https://gitea.treehouse.systems/jmercan/dumb-jose.

Language:GoLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

etu-coursebase

etu-coursebase

Language:PythonLicense:NOASSERTIONStargazers:0Issues:0Issues:0

embench-iot

The main Embench repository

License:GPL-3.0Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

etu-tvl

Interpreter implementation for a three-valued logic language

Language:MakefileStargazers:0Issues:0Issues:0

euro2016

2015-2016 Summer BIL 143 Homework 4

Language:CStargazers:0Issues:0Issues:0

gem5

The official repository for the gem5 computer-system architecture simulator.

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

lua-astronomical-almanac

Lua bindings for Astronomical Almanac (AA) a.k.a Moshier Ephemeris.

Language:CStargazers:0Issues:0Issues:0

mimalloc

mimalloc is a compact general purpose allocator with excellent performance.

License:MITStargazers:0Issues:0Issues:0

nandgame-sv

Experimental

Language:SystemVerilogStargazers:0Issues:0Issues:0

null-ls.nvim

Use Neovim as a language server to inject LSP diagnostics, code actions, and more via Lua.

Language:LuaLicense:NOASSERTIONStargazers:0Issues:0Issues:0

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

License:MITStargazers:0Issues:0Issues:0
Language:AssemblyLicense:Apache-2.0Stargazers:0Issues:0Issues:0

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

riscv-opcodes

RISC-V Opcodes

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

riscv32-decoder

A RISC-V instruction decoding library supporting 32-bit Integer (I), Multiply/Divide (M), Compressed (C), and Control and Status Register (Zicsr) instruction set extensions.

Language:C++Stargazers:0Issues:0Issues:0
Language:C++Stargazers:0Issues:1Issues:0

riscv32-sim-common

Shared data structures and utilities for decoding RISC-V instructions and exporting hart states across the riscv32-sim, riscv32-cosim-model, and riscv32-decoder projects.

Language:C++Stargazers:0Issues:0Issues:0

specni

An application which assesses planetary dignities/debilities based on Lilly's table given on p.115 of Christian Astrology

Language:C++Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

vim-snippets

My snippets

Language:Vim SnippetLicense:MITStargazers:0Issues:0Issues:0

xv6-riscv

Xv6 for RISC-V

License:NOASSERTIONStargazers:0Issues:0Issues:0