Weird layerSetup in SparkFun-4-layer-PCBWAY-LIMIT.dru
PaulZC opened this issue · comments
We should think about changing the layerSetup in SparkFun-4-layer-PCBWAY-LIMIT.dru. It is currently set to:
layerSetup = ([15:(1*2)+15*16])
which makes it possible to define blind vias between layers 1&2 and 1&2&15.
Maybe that's as intended, but it seems a weird choice. I got caught out by this when I accidentally defined a 1&2&15 via for one of my layer 15 signal traces. Unsurprisingly, there was a bad joint between the trace and via as the board was fab'd as a standard 4-layer board.
The other 4-layer .dru's use:
layerSetup = ((1*2)+(15*16))layerSetup = (1*2*15*16)layerSetup = (1+2*15+16)
I believe this was fixed when we updated our DRC files to JLCPCB:
