Soroush Sherafat's repositories
UdpPeerToPeerJustStun
a simple STUN server and a peer messenger application for peer-to-peer connection over UDP using NAT hole punching.
vjudge-cli
a command-line tool for automatic judge of verilog HDL code.
BranchPredictionSimulationJudge
an automatic judge for implementation of different branch prediction algorithms.
JalaliDatePicker
A lightweight and simple jalali datepicker. powerful javascript datepicker with no dependencies
ResidenceMocker
a database schema and a C# console application that inserts mocked data into the database.
search-engine-react
a simple search engine front-end, using React and Bootstrap.
choco
Chocolatey - the package manager for Windows
CodeMazeGuides
The main repository for all the Code Maze guides
digital_video_introduction
A hands-on introduction to video technology: image, video, codec (av1, vp9, h265) and more (ffmpeg encoding). Translations: 🇺🇸 🇨🇳 🇯🇵 🇮🇹 🇰🇷 🇷🇺
docs
OpenBMC Documentation
fwanalyzer
a tool to analyze filesystem images for security
most_stupid_qa_bot
the most stupid Q&A bot that could possibly exist, implemented using Flask.
numeric
Numeric library for the numeric calculations course. I'll try to add new features and keep this thing up-to-date with the course.
verilogen.py
a new method for verilog HDL code generation by templates, implemented using python and jinja2.
ComputerArchitectureLaboratory
solutions and reports for the Computer Architecture Laboratory course.
Hardwar-JavaPredictor
a template repository for automatic judge of Java branch prediction simulation code, using GitHub Actions.
Hardwar-VerilogPredictor
a template repository for automatic judge of Verilog branch prediction simulation code, using GitHub Actions.
iot-dashboard
a simple IoT Django dashboard.
ReflectivePolymorphism
do you want to use polymorphism but can't reference derived types at compile time?
twitter-sensitive-media
a Chrome extension that marks Twitter media as sensitive based on a blacklist of words.
vjudge-server
a server that uses GitHub's webhooks for automatic judge of verilog HDL code.