song0712's repositories
912_project
清华大学计算机系考研攻略 Guidance for postgraduate entrance examination in Department of Computer Science and Technology, Tsinghua University
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
avatarify-python
Avatars for Zoom, Skype and other video-conferencing apps.
awesome-c-cn
C 资源大全中文版，包括了：构建系统、编译器、数据库、加密、初中高的教程/指南、书籍、库等。
awesome-cpus
All CPU and MCU documentation in one place
C
C语言学习项目
CS-Books
超过1000本的计算机经典书籍、个人笔记资料以及本人在各平台发表文章中所涉及的资源等。书籍资源包括C/C++、Java、Python、Go语言、数据结构与算法、操作系统、后端架构、计算机系统知识、数据库、计算机网络、设计模式、前端、汇编以及校招社招各种面经~
DesignPattern
This repository is built for design pattern in C++
e200_opensource
The Ultra-Low Power RISC Core
ExtremeDV_UVM
UVM resource from github, run simulation use YASAsim flow
FPGA
FPGA
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
fpgahdl_xilinx
(RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products
hello-algorithm
🌍「算法面试+算法知识」针对小白的算法训练 | 还包括：1、阿里、字节、滴滴 百篇大厂面经汇总 2、千本开源电子书 3、百张思维导图 （右侧来个 star 吧 🌹，English version supported）
hw
RTL, Cmodel, and testbench for NVDLA
ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
LoongsonCsprj2017
Computer System Project for Loongson FPGA Board in 2017
mips-cpu
MIPS CPU implemented in Verilog
NaiveMIPS-HDL
Naïve MIPS32 SoC implementation
no-OS
Software drivers for systems without OS
nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
USTC-Course
:heart:**科学技术大学课程资源
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
vp_awsfpga
Virtual Platform for AWS FPGA support
zju-icicles
浙江大学课程攻略共享计划