SirHao / Artix-7-Verilog-LED-ADD-SUBSTRACT

operation of add and subtract

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ARTIX-7 数码管实现加减法运算

LED7TEST.srcs\constrs_1\new ：约束管脚，其中时钟clk为E3；

LED7TEST\LED7TEST.srcs\sources_1\new：全加/减器模块：OperatorAS

数码管以及输入调用全加/减器：LEAD7TEST

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operation of add and subtract

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