sifive / sifive-blocks

Common RTL blocks used in SiFive's projects

sifive/sifive-blocks Issues

Documentation?
Updated a year ago2
Arty100TShell - Connecting GPIOPMOD
Closed 2 years ago2
Add a new SPI IO port
Updated 2 years ago
Chiplink Assertion Failed
Closed 3 years ago8
gpio connection with Rocket Chip
Updated 4 years ago2
problem: the code generated by rocket-chip with i2c
Updated 4 years ago3
usage of spi flash
Closed 5 years ago
how to generate pwm.scala to RTL?
Updated 5 years ago1
PWM internal registers don't have reset
Closed 5 years ago1
How to modify periphery to use other clock and cross clock
Updated 6 years ago4
simulation and waveform
Updated 6 years ago
add package.json manifest
Closed 6 years ago
chiplink causing compile errors with chisel in latest rocket-chip
Closed 6 years ago3
A problem of the reset signal
Updated 6 years ago
uartRx won't sample after sample_mid
Updated 6 years ago
Octal SPI
Closed 7 years ago2