Shashank Shivashankar's repositories
square-root-design
This repo consists of a synthesizable square root design based on the Newton Raphson method.
Language:Verilog000
Asynchronous-FIFO
A simple 16-location 8-bit FIFO with different clock domains for Read and Write
Language:Verilog000
Simple-D-flip-flops-
Basic D-flip flops
hello-world
Just some stuff
trojans
Test demo for github.
Language:Shell000