Shrihari G (shariethernet)

shariethernet

Geek Repo

Location:United States

Home Page:shrihari.technowiz.org

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Organizations
TL-X-org

Shrihari G's repositories

siliconcompiler_sandpiper_saas_example

Example of using SiliconCompiler with Sandpiper-SaaS as the Frontend

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warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

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algebraic-nnhw

AI and matrix multiplication accelerator architectures requiring half the multipliers

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caffe

Caffe: a fast open framework for deep learning.

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CPlusPlus20FundamentalsLiveLessons

Source code examples for our **C++20 Fundamentals LiveLessons** Videos

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cpu_fpga

Implement all instructions for RISC-V including Branch instructions. This repository will provide the automation flow for running the design into hardware.

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custom_zynq_1

AXI4 Lite Slave - Zynq based Design

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darknet_ab

YOLOv4 / Scaled-YOLOv4 / YOLO - Neural Networks for Object Detection (Windows and Linux version of Darknet )

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edalize_18_6

An abstraction library for interfacing EDA tools

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edalize_sandpiper_example

Example for using sandpiper with edalize front-end

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fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

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gf_cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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mltk

A Python package with command-line utilities and scripts to aid the development of machine learning models for Silicon Lab's embedded platforms

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my_edalize

Edalize - WIP support for additional tools and flows

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OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

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QEMU_SystemC_app

Sample ARM application for QEMU/SystemC-based HW/SW Co-Simulation

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Retrieval-based-Voice-Conversion-WebUI

Voice data <= 10 mins can also be used to train a good VC model!

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riscv_myth_fpga

For use in RedwoodEDA's MYTH course

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sauria

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

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siliconcompiler

A modular build system for hardware

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Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

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