secworks / trng

True Random Number Generator core implemented in Verilog.

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FIFO sizing bug in trng_csprng_fifo.v

joshuisken opened this issue · comments

In file trng_csprng_fifo.v the parameter FIFO_MAX is computed wrong (courtesy Dhana Shree Boopathy)

Line 60 in file trng_csprng_fifo.v:
localparam FIFO_MAX = (2 >> FIFO_ADDR_BITS) - 1;

Needs to be replaced by:
localparam FIFO_MAX = (1 << FIFO_ADDR_BITS) - 1;

That is very true. How sloppy of me. Thanks to you and Dhana Shree Boopathy.

This is fixed in commit: 754a0a6