Sai TJ Bodanki's repositories
aleth
Aleth – Ethereum C++ client, tools and libraries
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
darknet
Convolutional Neural Networks
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
fairgame
Tool to help us buy hard to find items.
finn
Dataflow compiler for QNN inference on FPGAs
gemmlowp
Low-precision matrix multiplication
hive-flasher
Hive OS Drive Flashing Utility
HLS
Vitis HLS LLVM source code and examples
linux-socfpga
Linux development repository for socfpga
netron
Visualizer for neural network, deep learning, and machine learning models
nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
open-nic-shell
AMD OpenNIC Shell includes the HDL source files
OpenFPGA
An Open-source FPGA IP Generator
pcileech
Direct Memory Access (DMA) Attack Software
python-mini-projects
A collection of simple python mini projects to enhance your python skills
random_number_assessment
This repository is meant for instructions and scripts for random data assessment suite usage.
RapidWright
Build Customized FPGA Implementations for Vivado
riffa
The RIFFA development repository
udemy-downloader
A Udemy downloader that can download lectures, with DRM support.
VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
XilinxTclStore
Xilinx Tcl Store
yosys
Yosys Open SYnthesis Suite