ruishihan's repositories
documents-1
riscv.github.io
MachineLearning
Machine learning resources，including algorithm, paper, dataset, example and so on.
riscv-boom
BOOM: Berkeley Out-of-Order Machine
bitcoin
Bitcoin Core integration/staging tree
chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
chisel-testers
Provides various testers for chisel users
chisel-testers2
Repository for chisel3 testers2 open alpha
chisel3
Chisel 3: A Modern Hardware Design Language
diagrammer
Provides dot visualizations of chisel/firrtl circuites
firrtl-interpreter
A scala based simulator for circuits described by a LoFirrtl file
freedom
Source files for SiFive's Freedom platforms
gcc-toolchain-builder
Scipt collection to build GCC cross and/or native toolchains
H264BSAnalyzer
H264(AVC) and H265(HEVC) bit stream Analyzer, VS2010 MFC project(Windows 7 x64).
hosts-2
镜像：https://coding.net/u/scaffrey/p/hosts/git
migen
A Python toolbox for building complex digital hardware
myhdl
The MyHDL development repository
nmigen
A refreshed Python toolbox for building complex digital hardware
progASICp4SWITCH
progASICp4SWITCH
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
rocket-chip
Rocket Chip Generator
SimpleH264Analyzer
开源H.264码流分析器，主要用于H.264编码标准算法说明
SpinalHDL
SpinalHDL core
symbolator
HDL symbol generator
treadle
Chisel/Firrtl execution engine
u-boot-xlnx
The official Xilinx u-boot repository
veriloggen
Veriloggen: A library for constructing a Verilog HDL source code in Python
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
wujian100_open
IC design and development should be faster，simpler and more reliable