Feature support for Floating point extensions(`FD`).

[Pawan Kumar Sanjaya]

• fcsr & rm in coverpoints - The current coverpoints define effective rm fields i.e insts always have 7 and fcsr has the necessary rm. Future coverpoints will try to test the frm and rm fields individually to see if the rm field of the instruction over-rides the frm value at run time. To support this and the highlighted issue with fflags, the coverpoints will be modified to have conditions defined on the fcsr value along with the rm field of the instruction.
• Nan prefix in coverpoints - Add a new variable in the coverpoints which is defined as the 32 bit msb(in FD) of the value in the register. This is relevant because for most of the floating-point instructions if this prefix is not all 1's, the input is a canonical NaN. Hence the coverpoints should capture this particular aspect while describing cases for fadd.s in RV*FD. Current coverpoints will just have a condition(nan_prefix == 0xffffffff) appended to it.​
• DPR update - Current DPRs only test whether 1 signature update per instruction which hits coverpoints is present. This will be modified to vary from instruction to instruction by maintaining a mapping which tells the number of stores to the memory for each case. ​
• fcvt.*.* coverpoints (Caught by @davidharrishmc) - The coverpoints for the fcvt.a.b instructions currently assume that the target format is b whereas the target format is a. These need to be reworked. The current tests have a wrong coverage definition and hence provide no value. All outputs are NaNs.

[Pawan Kumar Sanjaya]

Added support in #47