Ricardo's repositories
Computer-Science-Textbooks
Collect some CS textbooks for learning.
writing-your-first-riscv-simulator
《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
riscv-isa-sim
Spike, a RISC-V ISA Simulator
PLCT-Open-Reports
PLCT实验室的公开演讲，或者决定公开的组内报告
XiangShan
Open-source high-performance RISC-V processor
oscpu-framework
A Verilator-based demo.
hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Helmet-Detection
This project is a proof-of-concept, trying to show surveillance of roads for the safety of motorcycle and bicycle riders can be done with a surveillance camera and an onboard Jetson platform.
riscv-isa-manual
RISC-V Instruction Set Manual
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
chisel3
Chisel 3: A Modern Hardware Design Language
hwacha-template
Template for projects using the Hwacha data-parallel accelerator
e200_opensource
The Ultra-Low Power RISC Core
riscv-tools
RISC-V Tools (ISA Simulator and Tests)
RV32
verilog RV32 cpu (CS3410)
CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++
mips-32bit
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
libpku
北京大学课程资料整理
USTC-CS-Courses-Resource
:heart:**科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)
vue_start
IT includes a vue2 webapp and a server writed by node.js
my-movies
use angular7 to build a weapp.
zero-riscy
zero-riscy CPU Core
hello-world
Just guidence
LeNet_Cpp_Remake
Simplified LeNet-5 with C++ based on x86 & RISC-V