rftafas

stdcores

Standard and Curated cores, tested and working.

hdltools

Python VHDL code generators

genesis

stdblocks

A collection for basic digital implementations used for building more complex IPs.

stdexpert

A numeric_std compatible replacement for std_logic_arith and std_logic_unsigned

fpga_toolkit

hdl_string_format

VHDL package to provide C-like string formatting

hdlparse

Simple parser for extracting VHDL documentation

maxino

physical_layer_crypto

vhls

VHDL High Level Synthesis is a library with some constructions to enable higher level usage of VHDL. Should work on synthesis.

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.