qicny

AutonomousDrivingCookbook

Scenarios, tutorials and demos for Autonomous Driving

bullet3

Bullet Physics SDK: real-time collision detection and multi-physics simulation for VR, games, visual effects, robotics, machine learning etc.

caliko

The Caliko library is an implementation of the FABRIK inverse kinematics algorithm in Java.

chrono

C++ library for multi-physics simulation

DAPLink

Deep-reinforcement-learning-with-pytorch

PyTorch implementation of DQN, AC, ACER, A2C, A3C, PG, DDPG, TRPO, PPO, SAC, TD3 and ....

DeepRL

Modularized Implementation of Deep RL Algorithms in PyTorch

Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

gpt-2

Code for the paper "Language Models are Unsupervised Multitask Learners"

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

libxcam

libXCam is a project for extended camera(not limited in camera) features and focus on image quality improvement and video analysis. There are lots features supported in image pre-processing, image post-processing and smart analysis. This library makes GPU/CPU/ISP working together to improve image quality. OpenCL is used to improve performance in different platforms.

litmus-tests-riscv

RISC-V architecture concurrency model litmus tests

Mask_RCNN

Mask R-CNN for object detection and instance segmentation on Keras and TensorFlow

maskscoring_rcnn

Codes for paper "Mask Scoring R-CNN".

Mathematics

数学知识点滴积累 矩阵 数值优化 神经网络反向传播 图优化 概率论 随机过程 卡尔曼滤波 粒子滤波

MVision

机器人视觉 无人驾驶 VS-SLAM ORB-SLAM2 深度学习目标检测 yolov3 行为检测 opencv PCL 机器学习移动机器人

nomeroff-net

Nomeroff Net. Automatic numberplate recognition system.

PhysX

NVIDIA PhysX SDK

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-probe

Simple machine mode program to probe RISC-V control and status registers

riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

ShiYanLou

学习C & C++ & python&汇编语言 数据结构 算法 操作系统 单片机 linux 面试

svunit-code

swerv-ISS

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

swerv_eh1_fpga

FPGA reference design for the the Swerv EH1 Core

therobotrix

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Zybo-Z7-20-pcam-5c