How to run the design for a specfic application

[Jianming]

Hi, thanks for opening the valuable work.

I have a hard time figuring out how to run the OpenCGRA. might I ask how to run the CGRA to launch CL, FL and RTL level simulation and generate RTL for any application?

Thanks in advance.
JT

[Cheng Tan]

Hi Jianming,

Thanks for your interest~!
For Verilog generation, you can just run pytest --tb=short -sv CGRARTL_test.py in the folder. Note that you need to first activate the virtual environment, install a specific version of PyMTL3, and install pytest as shown in the README.
For simulation, a mapping of the FIR kernel can be found here. CGRACL_FIR_demo_test takes the control signals for simulation.

Best,
Cheng