pbing / J1_BSV

Forth CPU J1 in Bluespec SystemVerilog (BSV)

Description

J1 Forth CPU core rewritten in Bluespec SystemVerilog (BSV) from Verilog Source.

Quickstart

Create an environment for BSC

source env.sh

Compile Forth program

make -C fs sim

Simulate

bsc -sim -u ./test/Tb.bsv
bsc -sim -e mkTb
./bsim

Create RTL

bsc -verilog -u ./src/J1.bsv

References

• James Bowman, Willow Garage, "J1: a small Forth CPU core for FPGAs"
• Arvind, "Non-pipelined processors", 2016
• Arvind, "Non-pipelined processors", 2019