DMSBoard: Implement Shift Register Abstraction Layer
pmalessa opened this issue · comments
Overview
The DMS 0.1.0 Board utilizes 2 serially concatenated shift register to extend its GPIO capabilities. A few Pins have been moved from GPIO Pins on the SAM into this shift register and many more have been added.
An Abstraction Layer shall be implemented to be able to set individual GPIOs on this shift register as if it is a normal GPIO.
Pin Definitions
The Shift Register are connected as followed:
| SAM Pin | Function |
|---|---|
| PC5 | Data |
| PC6 | Clock |
| PC7 | Strobe |
16 Bits can be controlled, from which some are reserved for future use:
| Bit | Function |
|---|---|
| 16 | DAC On |
| 15 | SPI Ch2 - unused |
| 14 | SPI Ch1 |
| 13 | SPI Ch0 |
| 12 | QSPI CS3 - unused |
| 11 | QSPI CS2 - unused |
| 10 | QSPI CS1 |
| 9 | QSPI CS0 |
| 8 | UB4 On - unused |
| 7 | UB3 On - unused |
| 6 | UB2 On - unused |
| 5 | UB1 On |
| 4 | IEPE4 On |
| 3 | IEPE3 On |
| 2 | IEPE2 On |
| 1 | IEPE1 On |
Details
- LSB has to be transmitted first
- Shift Register IC: 74HC595
I'd like to ask for what IEPE 1-IEPE 4 stand for?
Also about QSPI CS0, QSPI CS1 - do they work the same way like SPI Ch0, SPI Ch 1,mean addressing chip 1-chip 4?
IEPE1-4 enables the U_Bridge for each channel separately. The same functionality as was previously done by PC07 on SAM can now be done via the shift register for each Input channel.
The QSPI CS Pins work differently. They are directly connected to the CS Pins of the 2 chips. Therefore, you have to make sure to enable only one at a time
Wheres the difference between issue_85_86 and issue_85_86_ref branch?
Is the doc updated? Couldn't find it. Thanks!
The main difference is some refactoring ( issue_85_86_ref) was made for nodeControl and working with separate measurement channels.
The documentation is completed in my opinion if I didn't miss something