OpenRISC

mor1kx

mor1kx - an OpenRISC 1000 processor IP core

or1200

OpenRISC 1200 implementation

orpsoc-cores

Core description files for FuseSoC

or1ksim

The OpenRISC 1000 architectural simulator

tutorials

OpenRISC Tutorials

linux

Linux kernel source tree

or1k_marocchino

OpenRISC processor IP core based on Tomasulo algorithm

llvm-or1k

LLVM backend for OpenRISC 1000

newlib

newlib OpenRISC development

or1k-gcc

GCC port for OpenRISC 1000

or1k-src

OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)

openrisc.github.io

Source for openrisc.io

doc

Misc documentation and specifications

or1k-tests

Unified OpenRISC 1000 test suite

clang-or1k

Clang for OpenRISC 1000

ompic

Open Multi-Processor Interrupt Controller - for OpenRISC

binutils-gdb

Binutils and gdb fork for OpenRISC

old-openrisc-svn

Copy of the old OpenCores OpenRISC Subversion

barebox

OpenRISC fork of barebox

musl-cross

A small suite of scripts and patches for building musl libc cross compilers.

or1k-glibc

glibc port for or1k

intgen

An verilog core for testing CPU interrupts

or1k-tcltools

community-wiki

Community Wiki clone

mor1kx-generic

mor1kx OpenRISC generic test harness support verilator and iverilog

rtems-source-builder

Fork of the RTEMS source builder (RSB)

gcc

This is not the project you are looking for check openrisc/or1k-gcc.

libunwind-or1k

Zero-cost (Itanium ABI) exception handling library for OpenRISC 1000

or1k-headers

OR1K Common Headers

uClibc-or1k

uClibc for OpenRISC 1000