aspeed: implement a reset driver
legoater opened this issue · comments
To reboot the Aspeed SoCs, the Linux kernel depends on settings being done in the OpenBMC U-Boot.
It is currently broken if a mainline U-Boot is used.
Linux needs a reset driver taking into account the reset mask of the watchdog.
I'm a bit confused by this one. Reset drivers in Linux thus far are for turning off and on IP blocks.
Resetting the SoC is usually done by the watchdog. We already have a bunch of things in there to control the reset policy. Could we fix up/extend the watchdog to cover this requirement?
Yes. We also need to take into account the reset mask of the watchdog on the AST2500. It is modified by the mainline U-Boot and this breaks reset on Linux.
The reset devices are today registered in the clk driver. Is there a reason for doing so and not having a
standalone reset driver for Aspeed SoC ?
The reset and clock enable is closely tied together. In order to enable a piece of IP the aspeed datasheet specifies this sequence:
- Disable clock
- Release reset line
- Wait 5ms
- Enable clock
We could have attempted to have two separate clock and reset drivers, but it would have been messy connecting them together. As most of the clocks have a one to one relationship with reset lines and IP blocks, there was no reason to have them separate.
This thread contains some of the discussion from back when we merged the clock driver:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-April/423931.html