Naveen R's repositories
FriedRiceLab
Official repository of the Fried Rice Lab, including code resources of the following our works: ESWT [arXiv], etc. This repository also implements many useful features and out-of-the-box image restoration models.
PDPU
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
RDST
Official implementation of RDST. A residual dense swin transformer for medical image super-resolution
ViTALiTy
ViTALiTy (HPCA'23) Code Repository
ArSSR
[IEEE J-BHI] An Arbitrary Scale Super-Resolution Approach for 3D MR Images using Implicit Neural Representation
AHB2APB-PROTOCOL-BRIDGE
The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB
AHB-to-APB-Bridge
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
32-Verilog-Mini-Projects
verilog utils
CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
16bit-RISC-Processor-Design
The Goal of this project is to design an 16-bit RISC Processor which is capable of handling programs like the Fibonacci number calculator. The Designed processor is then implemented in a Spartan-6 FPGA. The input from the switches (in binary) will be used to find the nth Fibonacci Number, which is displayed in the 7-segments/LED's.
Deep-Learning-Papers-Reading-Roadmap
Deep Learning papers reading roadmap for anyone who are eager to learn this amazing tech!
Neural-Networks-on-Silicon
This is a collection of works on neural networks and neural accelerators.
Convolutional-Neural-Network
Implementation of CNN using Verilog
async-fifo
Asynchronous FIFO for transferring data between two asynchronous clock domains