Names with dots not rendered.
Zottel opened this issue · comments
When I render circuits with input/output names containing dots, i.e. from SystemVerilog interfaces, these names are not rendered. Is this a bug or intended behaviour? Is there a way to escape these names or should I remove them from my output?
Looking forward to your reply and thank you for the awesome tool :)
something.withoutdots.json.txt
netlistsvg uses periods internally for some internal naming so I'm guessing that must've confused it. I didn't intend not to support names with dots though so I suppose it's a bug.