Wires overlap for simple drawing.
joseluisquiroga opened this issue · comments
The wires for first and last ports overlap as if they were a single wire for the json code generated.
The json code was generated with the following command:
yosys -p "read_verilog recu.v; prep -top unary_nand -flatten; aigmap; write_json recu.json"
For the file recu.v containging the following code:
Verilog
module unary_nand
#(parameter WIDTH = 32)
(input [WIDTH-1:0] in_and,
output out_and);
generate
if(WIDTH == 1) begin
assign out_and = in_and;
end
else if(WIDTH == 2) begin
assign out_and = in_and[0] & in_and[1];
end
else begin
unary_nand #(.WIDTH (WIDTH/2))
unary_nand_low
(.in_and (in_and[WIDTH/2-1:0]),
.out_and (out_and_low));
unary_nand #(.WIDTH (WIDTH - WIDTH/2))
unary_nand_high
(.in_and (in_and[WIDTH-1:WIDTH/2]),
.out_and (out_and_high));
assign out_and = out_and_low & out_and_high;
end
endgenerate
endmodule
The json code is:
Json file
{
"creator": "Yosys 0.9+932 (git sha1 613334d9, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os)",
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"top": 1,
"src": "recu.v:4"
},
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"direction": "input",
"bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ]
},
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"direction": "output",
"bits": [ 34 ]
}
},
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Could you put your code in a:
<details><summary>whatever.json</summary>long code here</details>
I think this is closer to what you were wanting (even if I can't see what you originally had), though there are still a few overlapping wires around the edges of the split block. This is with a newer version of ELKjs.
duplicate #105