nqHITSZ's repositories
Systolic-Array
course design
convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
Systolic_Array_FIR
Implementation of a FIR filter based on Systolic Array using Verilog
verilog-axis
Verilog AXI stream components
AdderTreeGenerateScript
A python script for generating Parameterizable AdderTree(unsigned) verilog module.
Systolic-Array-1
Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
systolic-array-sorting
Implementation of a Systolic Array based sorting engine using Verilog