how to run the code in armv8-a?

[yexiansheng]

can you tell me how to run the code in armv8-a?
I have compiled the code as you described, and my platform is also armv8（raspberry-4b ARM-A72 ubuntu）. However, why is it not running correctly?

I have also tried running the corresponding SHA256 code on the x86 architecture, and it still generates the same type of error.

Could you help me find and correct the error, please?

[Jeffrey Walton]

You need a processor with the ISA support.

For example, this is from an armv8.1 machine with Crypto extensions. Notice sha1 sha2.

> cat /proc/cpuinfo 
processor       : 0
BogoMIPS        : 500.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x1
CPU part        : 0xd07
CPU revision    : 2

This is from a Intel Goldmont machine. Notice sha_ni.

$ cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 92
model name      : Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
stepping        : 9
microcode       : 0x48
cpu MHz         : 1055.627
cache size      : 1024 KB
physical id     : 0
siblings        : 4
core id         : 0
cpu cores       : 4
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 21
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov 
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdt
scp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology tsc_reliab
le nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_c
pl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_d
eadline_timer aes xsave rdrand lahf_lm 3dnowprefetch cpuid_fault cat_l2 ibrs ibp
b stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust smep er
ms mpx rdt_a rdseed smap clflushopt intel_pt sha_ni xsaveopt xsavec xgetbv1 xsav
es dtherm ida arat pln pts md_clear arch_capabilities
vmx flags       : vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ep
t_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest v
apic_reg vid ple shadow_vmcs

On Linux, you should guard the accelerated code paths with something like https://github.com/google/cpu_features . If the ISA is not available, then fall back to C/C++.

[yexiansheng]

ok，thanks a lot

[yexiansheng]

I apologize for bothering you again, but I encountered another issue during my attempts. I tried running the executable file on a development board that supports SHA with armV8 architecture. However, it seems that the program cannot run on this board. Additionally, I tried running another Neon program (test3 in the figure) that does not use SHA, and it ran successfully. Based on this, I suspect that the problem is related to the SHA instructions.

Could you please provide me with some hints or assistance? Furthermore, since the armv8 development board does not have GCC installed, I compiled the code on a Raspberry Pi 4B and then attempted to run it on the development board. I believe the compilation command remained unchanged, so it should not be the cause of the issue. Nonetheless, I sincerely appreciate the code you shared.

compile the code on a Raspberry Pi 4B

want to run the code in the development board that supports SHA with armV8

[yexiansheng]

ohhhhh！
I found the reason and the solution! I added the "-static" option for static compilation, and it resolved the issue. Now, I can successfully run the program on the ARMv8 development board that supports SHA. Thank you so much!