The repository provides one way to realize single-cycle CPU with verilog_VHDL.
The development enviroment is QUARTUS 12.SP1 in Windows.
All .v file are the source code for the single-cycle CPU.
The testbench data is in the simulation file ,whose filetype is named is *.vt.
You can try it at your own risks! Have fun!
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It is my first commitment!