Missing FCLK_CLK1 output to XOUT.0 (pin U18)
jonny5532 opened this issue · comments
My EBAZ4205 board has no crystal oscillator for the ethernet PHY, but instead has R1485 populated, and the FPGA needs to provide the 25MHz clock from pin U18.
To make the ethernet work I had to output FCLK_CLK1 (which needs be configured as a 25MHz clock) to pin U18 (which needs to be configured as an output).
Adding this here in case it is useful for anyone else - I can raise a PR with the addition if you like.
Is this the only change to this repo to make ethernet work?
No changes to the device tree?
Raising a PR would be useful - there are many of these boards around but no-one has documented how to get one without the crystal working!
I'm currently still using the original firmware, which seems to configure that clock at boot. I'm then loading custom bitstreams over serial/ethernet and catting them to /dev/xdevcfg (I don't have a spare SD card or suitable JTAG cable currently).
I presume the FSBL and/or DTS will need regenerating - hopefully enabling the FCLK_CLK1 at 25mhz via the Zynq wizard and then regenerating all the intermediaries would be enough (as well as the FCLK_CLK1->U18 connection).
I don't have Vivado 2018.3.1 handy currently and also (due to lack of SD card) can't load new firmware anyway, so someone else might be better placed to test that.
I have this working now - as you say, just set up the clock, make it external and assign the pin and it works!