RISC-V Processor written in Veryl.
bluecore is 5-stage in-order core supporting subset of RV32I.
Veryl version is latest on master branch.
$ git clone https://github.com/nananapo/bluecore
$ git submodule init
$ git submodule update
$ make build
- rv32ui-p-*
$ make verilator MEMFILE=test/riscv-tests-bin/rv32ui-p-add.bin.hex CYCLE=0
...
wdata: 0000000000000001
test: Success
RV32I is selected as default. You can change ISA by change config.
bluecore/core/src/PackageConf.veryl
Lines 1 to 2 in 353b16a
synth/gowin/
directory is GOWIN FPGA Designer project.
You can synthesize bluecore on TangMega 138K Pro Dock (GW5AST).
Change SYNTHESIS_GOWIN=0
to 1
in core/src/PackageConf.veryl
and run make build
before open projects.