gustavonmartins / piscado

Risc V simulator done in Python during Twich Live coding!!!

Implements a subset of Risc V ISA in Python, for educatinal purposes

Is is being developed with live streaming on Twitch and Youtube, with friends from Risc V Brazil Telegram Group

Useful documentation:

• For basic architecture of CPU (PC, MAR, MDR, IR, etc):

  • https://cseweb.ucsd.edu/classes/fa13/cse140L-a/LAB4_tinycpu.pdf
  • https://elearning.algonquincollege.com/coursemat/abufarn/dat2343/chap_7.htm
  • https://www.youtube.com/watch?v=jFDMZpkUWCw

• Explanation of datapaths' five stages:

  • https://passlab.github.io/CSE564/notes/lecture08_RISCV_Impl.pdf
  • https://www.cs.cornell.edu/courses/cs3410/2019sp/schedule/slides/06-cpu-pre.pdf

• For a Risc V simulator:

  • http://tice.sea.eseo.fr/riscv/

• For generating Risc V assembly code:

  • https://godbolt.org/