The aim of this project is to create from scratch a GPU or 'graphics card' for my home-made uCOM computer (details of which will be available on a website sometime in the future!) This repo is a storage site for the HDL code used to describe the GPU itself and software tools that helped in its development.
When completed, the GPU will support text (via a VT100 compatible console) and graphics modes. The project is currently in development - see eevBlog for the latest developments and to follow along.
This repo contains the Verilog HDL code to create a VGA-, and later maybe HDMI-capable video driver using a compatible FPGA of your choice. You'll need to have a development board with a suitable FPGA with at least 50 KB of internal RAM for later development versions and the software to read the project - in this case Quartus II from Intel/Altera.
During early stages of development (for the text-mode design) however, you can get by on an Intel/Altera Cyclone II EP2C5T144C8 dev board, which can be had for less than £14 via everyone's favourite auction website - do a search for 'Cyclone II minimum development board'.
This repository contains a number of folders and not all are essential to get a GPU up and running, although the non-essential folders will no-doubt assist in getting it set up and facilitate testing and tweaking.
Primary folders are:
The main Quartus Prime project folder, specific to a particular version of FPGA.
Contains manuals, documentation and information on the project and its constituent parts.
Contains font files for use with the GPU.
Contains various Quartus II projects (yes, Quartus II - version 9.1) used for simulating and testing components of the project.
Contains the RS232 debugger, written by Brian Guralnick, which is an essential part of the setup and testing for the GPU, along with other key tools.
- A suitable FPGA development board - detailed above
- The project code in this repo
- An FPGA-compatible IDE for the FPGA to compile and upload the code (Quartus Prime)
- Note: If you're using a Cyclone II, Quartus II/Prime does not support this FPGA after version 13.0sp2
Please read CONTRIBUTING.md for details on code of conduct, and the process for submitting pull requests to me.
- nockieboy - Initial work - nockieboy
- BrianHG - thanks for your support, without which I'd still be struggling to get colour bars to display!
See also the eevBlog forum for the users who participated and contributed to this project, along with the discussion and development of the GPU.
This project is licensed under the MIT License - see the LICENSE.md file for details - although this may be reviewed later when I actually have to time to look at what the MIT licence actually is!
- Inspirational advice and tips from the many users of the eevBlog forums, including jhpadjustable, berni, asmi and many others