Morteza Rezaalipour (MortezaRezaalipour)

MortezaRezaalipour

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Location:Lugano, Ticino, Switzerland

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Morteza Rezaalipour's repositories

ErrorEval

This is the open source code for our paper titled "ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing"

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VerilogPADAnalyzer

VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

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JPEG_Encoder_VHDL

A Simple JPEG Encoder in VHDL

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Synthesizable-VHDL-Implementation-of-Cyclic-Codes

My BSc Project: Implementation & Evaluation of a cyclic code using FPGA

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VerilogChecker

A circuit equivalence checker given an error threshold for Approximate Computing

A-Simple-OpenCL-Project

A simple OpenCL project for parallel processing

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AxMAP

AxMAP: Making Approximate Adders Aware of Input Patterns

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helpful_vhdl_open_source

Simple VHDL examples using ghdl as compiler and wave generating

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