MINRES Technologies GmbH

SystemC-Components

A SystemC productivity library: https://minres.github.io/SystemC-Components/

DBT-RISE-RISCV

An instruction set simulator based on DBT-RISE implementing the RISC-V ISA

CoreDSL

Xtext project to parse CoreDSL files

SCViewer

Online documentation can be found at https://minres.github.io/SCViewer/

RDL-Editor

A Xtext based SystemRDL editor with syntax highlighting and context sensitive help

HIFIVE1-VP

A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS

DBT-RISE-Core

DBT-RISE - A versatile Dynamic Binary Translation (DBT) based environment to implement instruction set simulator (ISS)

PySysC

Public repository for the SC Common Practices Subgroup

TGC-VP

The Scale4Edge ecosystem VP

LWTR4SC

Lightweight transaction recording for SystemC

RISCV_ISA_CoreDSL

CoreDSL descriptions of the RISC-V ISA

conan-recipes

A bunch of conan recipes to package C++ libraries

conan-center-index

Recipes for the ConanCenter repository

crave

Constrained RAndom Verification Enviroment (CRAVE)

fc4sc-accellera

Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting.

gdbwave

GDB server to debug CPU simulation waveform traces

mlonmcu

Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends

mlonmcu-sw

Target software library (MLIF, Machine Learning Interface) used by the MLonMCU python package

NaxRiscv

PeakRDL-svd

Import and export CMSIS-SVD register models

proteus

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

pyucis

Python API to Unified Coverage Interoperability Standard (UCIS) Data

pyucis-viewer

QT-based viewer for UCIS coverage data

riscv-arch-test

riscv-opcodes

RISC-V Opcodes

RISCV-VP

SpinalHDL

Scala based HDL

TGC-ISS

This is a mirror of the TGC-ISS

tracy

Frame profiler

verilator

Verilator open-source SystemVerilog simulator and lint system