Project is provided as is and without any warranty
Currently only Digilent Arty board is supported
Tested with Vivado 2016.4
reference: https://github.com/riscv/riscv-gnu-toolchain
$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git
$ cd riscv-gnu-toolchain
$ git checkout v20170503
$ git submodule update --init --recursive
$ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev
$ ./configure --prefix=/opt/riscv32i --with-arch=rv32i
$ sudo make
reference: https://github.com/olofk/fusesoc
Use fusesoc modified by MIET work group
$ git clone git@github.com:miet-riscv-workgroup/fusesoc.git
$ cd fusesoc
$ git checkout current_xsim
$ sudo apt install python3-pip
$ sudo -H pip3 install -e .
$ git clone https://github.com/miet-riscv-workgroup/anthill
$ cd anthill
$ make -C sw/uart_bootloader
$ ./sw/generate_dat.py sw/uart_bootloader/uart_bootloader.bin sw/boot.dat
In the root directory of anthill project
$ fusesoc --cores-root . build anthill --g_riscv_firmware=boot.dat
$ git checkout current_xsim
$ sudo apt install python3-pip
$ sudo -H pip3 install -e .
Directory build will be created in current directory.
Resulting .bit file will be put in the ./build/anthill_0/bld_vivado/
$ make -C sw/serial_test
$ ./sw/uart_bootloader/boot_uart.py ./sw/serial_test/serial_test_bootable.bin /dev/USBtty0
Simulation can be done with following command:
$ fusesoc --cores-root . build anthill --g_riscv_firmware=boot.dat
Simulation output is vcd file anthill.vcd
It will be placed to ./build/anthill_0/sim-xsim/
Results can be viewed with GTKWave (install with sudo apt-get install gtkwave)