Michael's repositories
Vivado_Batch_Mode_Tool
A tool for those who want to use Vivado's batch mode more easily
General_Aurora_Intf
A simple example for using Aurora interface
.emacs.d
My emacs configuration
adapters
Common SOC interconnect protocols adapters for learning
axi
AXI4 and AXI4-Lite interface definitions and testbench utilities
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
gitignore
A collection of useful .gitignore templates
ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
open-rdma
RoCE v2 hardware implementation using Spinal HDL
openc910
OpenXuantie - OpenC910 Core
pcileech
Direct Memory Access (DMA) Attack Software
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
pulpino
An open-source microcontroller system based on RISC-V
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
spacemacs-private
My Spacemacs config
Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
SpinalHDL
Scala based HDL
SpinalTemplateSbt
A basic SpinalHDL project
tvip-axi
AMBA AXI VIP
verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
wujian100_open
IC design and development should be faster，simpler and more reliable
YASA
:snail:Yet Another Simulation Architecture