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meow-chip / MeowV64

A superscalar RISC-V CPU with out-of-order execution and multi-core support

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MeowV64

MeowV64 is a synthesizable and configurable superscalar RISC-V CPU with out-of-order execution, L1/L2 caches and multicore support. MeowV64 implements the RV64IMAFDCSU ISA.

Authors

See AUTHORS file

License

All code under this repository is released under the MIT license. See LICENSE file.

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A superscalar RISC-V CPU with out-of-order execution and multi-core support

License:MIT License

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