Mahesh Bhat K's repositories
ATPG_Tool_with-UI
Creating a end to end Open source Tool. Runs ATPG Algorithm(PODEM), Testablilty measures(SCOAP Analysis) for the Circuit created by user in Graphical User Interface
i2c_master_slave
Both read and write operation
covid-vaccine-booking
This very basic script can be used to automate COVID-19 vaccination slot booking on India's Co-WIN Platform. SET FOR BENGALURU
Language:Python000
RTL_to_GDSII_Adder
RTL to GDSII of a 64bit Adder
Language:Verilog000
Single_Cycle_Processor
A single cycle CPU has been constructed in Verilog.
DNS-using-Cisco-Packet-Tracer
DNS implementation using Cisco Packet Tracer Software in various configurations.
000
dvsd-12-Bit_Adder_Using_4-Bit_CLA
Designing a 12 Bit adder using 4 Bit CLA
000
Language:SCSS000
RealTimeClock
Real Time Clock(RTC) on 7-segment display.Implementation on FPGA
Language:Verilog000
RTL_Practice
Very simple basics using Verilog
UART
UART in Verilog.
Language:Verilog000