NothingSerious's repositories
awesome-cpus
All CPU and MCU documentation in one place
xv6-public
xv6 OS
xv6-riscv
Xv6 for RISC-V
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
xudailong.github.io
blog & blog theme🤘
qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
wujian100_open
IC design and development should be faster，simpler and more reliable
you-get
:arrow_double_down: Dumb downloader that scrapes the web
R8051
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
e200_opensource
The Ultra-Low Power RISC Core
swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
cores
Various HDL (Verilog) IP Cores
12306
12306智能刷票，订票
erpnext
Open Source ERP built for the web
DjangoBlog
🍺基于Django的博客系统
django-cms
The easy-to-use and developer-friendly CMS
SIS-Base-Edition-Python
Student Information System
LearnWebDiaries
A Web Learning Diaries From all of My Path
VirtualChatRoom
一个Python开发的虚拟聊天室
LearnCandCppDiary
学习C和C++笔记整理
LearnPythonDiary
Python学习笔记整理
SIS-Updated-Version
一个升级版的SIS。基于Python。
EasyNote1.3
Third edition of EasyNote
EasyNote
A simple project which about a note， bill， inventory and so on.
ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
TetrisGame
俄罗斯方块游戏开发教程实例代码