lxu28973's repositories
riscv-chisel
RISC-V CPU design using Chisel
Language:Makefile000
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:CBSD-3-Clause000
chisel-template
A template project for beginning new Chisel work
Language:Scala000
Language:Scala000
Language:Scala000
Language:Java000
computer-science
:mortar_board: Path to a free self-taught education in Computer Science!
MIT000
Halide
a language for fast, portable data-parallel computation
Language:C++NOASSERTION000
Language:ScalaBSD-3-Clause000
Language:CBSD-3-Clause000
Language:ScalaNOASSERTION000
riscv--verilog
RISC-V RV32I cpu simple design
Language:Verilog000
Language:Scala000
Language:HTML000