Luca Valente's repositories
culsans
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:AssemblyNOASSERTION000
hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
Language:SystemVerilogNOASSERTION000
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opensbi
RISC-V Open Source Supervisor Binary Interface
Language:CNOASSERTION000
rv_plic
Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)
Language:SystemVerilogApache-2.0000
Language:SystemVerilog000