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lnis-uofu / Caravel-QLSOFA-HD

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Caravel-QLSOFA-HD

Highlights

  • Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
  • Designed with Skywater130nm PDK with HD standard cell library
  • Base K4 architecture from VPR with 60 vertical and horizontal channels
  • Soft adder implementation
  • Designed using commercial PnR tool

Contribution

NOTE

  • This repository is created for The eFabless Open MPW shuttle program submission
  • The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel

About

License:Apache License 2.0

Languages

Language:Verilog 99.5%Language:Shell 0.2%Language:Tcl 0.1%Language:C 0.1%Language:Makefile 0.1%Language:Python 0.0%Language:Assembly 0.0%