lapd-soc / U500-freedom-altera

Porting U500-freedom to Altera FPGA (TR4 Board, SoCKit Board)

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This repository consist of:

  1. Quartus Prime cleaned tempalte projects for u500-freedom on TR4 and SoCKit Boards.
  2. Modified common.mk, it can automatically modify the u500-freedom-vc707 generated verilog code to be compatible with previous Quartus Prime tempalte projects.
  3. Guide Document that has detailed explaination for porting manually.

Quick instruction:

  1. Follow this repo and generate the u500-freedom-vc707 verilog and mcs files.
  2. Clone this repository.
  3. Replace the common.mk in the "freedom" directory with new one from this repository.
  4. Run "make" with the "altera_TR4" target. It will copy and make some needed modification to the generated files from step 1 and put them in "freedom/builds/altera_TR4_board" folder.
  5. Copy and add files in "freedom/builds/altera_TR4_board" folder to Quartus Prime Project.
  6. Do Full Compile Design in Quartus Prime project, then program the board and test as usual (as in u500-freedom vc707 prj).

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Porting U500-freedom to Altera FPGA (TR4 Board, SoCKit Board)


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Language:Verilog 93.3%Language:SystemVerilog 3.0%Language:C 1.2%Language:HTML 0.9%Language:Tcl 0.9%Language:Coq 0.6%Language:VHDL 0.1%Language:Shell 0.0%Language:Makefile 0.0%Language:Mathematica 0.0%Language:Forth 0.0%