Gateware Endpoint
zignig opened this issue · comments
Nice work so far,
I currently have a tinyfpgaBX and it only has direct connected USB pins , would it be possible to make this project expose the balance of the interface to pin only usb ?
We'd need to add a FS PHY for that. Is it what you are asking ?
I think so, the "phy" on the tinybx (and others) is two FPGA pins and a pullup.
https://github.com/m-labs/nmigen-boards/blob/master/nmigen_boards/tinyfpga_bx.py#L22
I think so, the "phy" on the tinybx (and others) is two FPGA pins and a pullup.
https://github.com/m-labs/nmigen-boards/blob/master/nmigen_boards/tinyfpga_bx.py#L22
We just added a FS transceiver that can drive two pins (with a pullup on D+) in 1f77745.
However, sampling a FS USB link requires at least a 48 MHz clock. We should probably make it support Low Speed too, since most iCE40 FPGA dev boards in nmigen-boards use a 12-16 MHz clock.
a PLL @ 48Mhz is possible on the tinybx. Thanks ! will investigate this weekend.
Attempt at version here.
https://github.com/zignig/tinybx_stuff/tree/master/usb
The max speed is a little low.
Info: Max frequency for clock 'pll_clk_$glb_clk': 36.54 MHz (PASS at 12.00 MHz)
Tried running it at 48Mhz anyway, load the image and dmesg tells me.
""
[253359.989222] usb 1-3.1.1.3: USB disconnect, device number 15
[253360.340850] usb 1-3.1.1.3: new full-speed USB device number 16 using ehci-pci
[253360.520864] usb 1-3.1.1.3: device descriptor read/64, error -32
[253360.808872] usb 1-3.1.1.3: device descriptor read/64, error -32
""
how much work is making a 12Mhz clocked usb ?
The amusing circular problem is that I need a usb sniffer.
More investigation,
Just the USBPHY clocks in at 56.27 Mhz.
Info: Max frequency for clock 'pll_clk_$glb_clk': 56.27 MHz (PASS at 12.00 MHz)
It may be possible to split the design into two clock domains, 1 for phy sampling and a second for USB internals.
edit , pll was not included
You can reduce the required 48Mhz to 24MHz using DDR sampling but you need to modify all the input/output logic.
ICE40 SB_IO
SB_IO documentation: http://www.latticesemi.com/view_document?document_id=52206
Interesting , will have a look.
@xobs has developed usb simulation models. You can use them for testing this modification.
Antmicro took that and ran with it, and ended up with https://github.com/antmicro/usb-test-suite-cocotb-usb
The Antmicro Cocotb USB test suite already supports multiple USB implementations (including the ValentyUSB stack). See https://github.com/antmicro/usb-test-suite-build
- valentyusb
- usb1_device
- tinyfpga's original stack
- ice40-playground
- etc....
Amazing! Thanks!
Currently covered by https://github.com/greatscottgadgets/luna , perhaps backporting to nmigen-stdio later