laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Add bit mask or count to AOM to enable modulo addressing and sliding windows

laforest opened this issue · comments

Related: #56

If we add a bit mask to the offset of the AOM, we could do DSP-like circular buffers in power-of-two sizes (and alignments? tied to pointer base address?). Cheap, but a little inflexible.

Alternatively, we can add a counter and a second Programmed Increment (PI): after N-1 accesses with increment I, the Nth access uses another increment J, which could be negative.
If J == I, then we have arbitrary circular buffers, of size limited by the counter.
If J == I-1, then we have a sliding window (e.g. for FIR filters)

Max cost: one 10/12 bit counter, and double the number of 10/12 bit PI entries.
We would have to store the extra PI as a separate memory fetched in parallel, one of which selected by a flag set by the counter before getting added to PO. Based on the improve Controller (fig 5.6, pg. 94 in thesis), a mux before the PO+PI adder, in the same pipeline stage, might be fast enough.

Note: this strongly interacts with #46, which would remove the multiplexers from the AOM design, and shorten them the one stage needed to fit them after pipeline stage 1.