Increase the number of branch condition flags
laforest opened this issue · comments
Currently, the BTMs support 8 conditions, based of a 3-bit binary flag selector.
Can we increase this to 16 without impacting Fmax?
Related: #40
Verilog FPGA Parts Library. Old Octavo soft-CPU project.
laforest opened this issue · comments
Currently, the BTMs support 8 conditions, based of a 3-bit binary flag selector.
Can we increase this to 16 without impacting Fmax?
Related: #40