laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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False no-ops and equivalent Boolean operations to hinder power side-channel

laforest opened this issue · comments

Related to #47, #48, and #35.

If the new no-op (see #45 and #35) becomes ADD, 0, 0, 0, and reduces power via Annul, then we could create false no-ops (e.g.: SUB 0, 0, 0), which don't raise Annul, and thus hide some power profiles of code execution.

Similarly, based on #35, we could switch the implementation of some bit-manipulation functions with Boolean-equivalent versions using different LUT instructions, also maybe hiding some power profiles.

Taking this further, if Annul shuts down unused FU stages (e.g. Adder when doing a Multiply), then perhaps we can selectively (pseudo-randomly?) inhibit that effect to also hide power profiles.

Also, we could make the I/O Handshaking module behaviour programmable to issue a variety of false no-ops (or even instructions with real and/or decoy side-effects) while waiting, so as to hide some I/O operations. In effect, extending I/O handshaking with a co-routine instead of a no-op.

This co-routine (a stored PC in the I/O Handshaking module?) could also emulate some of the work recovery aimed-at by thread re-scheduling on I/O latency events, which we strictly disallow in Octavo to maintain determinacy.