laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Add loop counters

laforest opened this issue · comments

Create a simple multi-threaded word-wide counter, mapped into High memory.
Assign one of the "fast compare" condition codes to the counter, high when counter == 0
A thread write a count value to the counter, and a BTM entry for its condition code.
Each time the BTM entry selects that condition, the counter decrements by one, saturating at zero (else we might fall into quasi-infinite loops by error, rather than 0-length ones).
The branch is taken when the counter == 0 before decrement.

Why? Since Octavo has already tight, reduced code, this will greatly improve loop efficiency. It's a common trick in DSPs, although less flexible than what the BTM enables.