laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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merge wren with data out to update only relevant data I/O register?

laforest opened this issue · comments

Currently, doing an I/O write updates all data registers, but only the wren for the updated I/O port changes, indicating where the data must go. This seems messy and maybe wasteful of power.

Now that fixing issue #38 adds a register stage, maybe we should use the wren signal to update only the data register of the same I/O port?

Add to this: there is a bug where the internal wren signal is only 1-bit wide, not WRITE_PORT_COUNT bits wide. This was hidden because most tests instantiate only one write port. Will change default to 2 or 4 ports.