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laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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I/O writes happen one cycle too early!!!

laforest opened this issue · comments

commented

Since I/O writes happen in stage 4, not 5, they are 7 cycles later than I/O reads, not 8.

Thus even a direct connection from I/O write to I/O read cannot pass data inside a single thread! More seriously: an external accelerator would have to do contortions to compensate.

Solution (being addressed in simd_refit branch): add one cycle delay to I/O data and wren outputs.