I/O writes happen one cycle too early!!!
laforest opened this issue · comments
Since I/O writes happen in stage 4, not 5, they are 7 cycles later than I/O reads, not 8.
Thus even a direct connection from I/O write to I/O read cannot pass data inside a single thread! More seriously: an external accelerator would have to do contortions to compensate.
Solution (being addressed in simd_refit branch): add one cycle delay to I/O data and wren outputs.