laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Turn off useless Quartus warning messages

laforest opened this issue · comments

See: http://quartushelp.altera.com/12.1/mergedProjects/hdl/vlog/vlog_file_dir_msg_onoff.htm

Basically, place a message_off directive at each module instance where synthesis reports warnings that don't help. Example: the lack of write ports on the inferred memory in the Address_Translator, and the width warnings for non-multiple-of-4-width memories.

That link is gone. As is the method of using a "message_off" directive.
You now right-click on messages in the GUI and suppress them.
This creates a .srf file which lists the patterns to suppress.
The suppressed messages end up in a .smsg file for each P&R stage.