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laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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ECC support in Cyclone V

laforest opened this issue · comments

commented

Cyclone V M10K BRAMs have 40-bit words and ECC support. Maybe leave Octavo architecturally at 36-bits (or somesuch), and use the ECC instead.

If that includes SECDED operation, then we could use the output of the ECC logic to detect a corrupt A/B/I read and if fixed (SEC), annul the instruction, store the corrected value(s) back into memory (might be stuck to the range of a double-move write), and re-issue later.

If not fixed (DED), then annul the instruction and jump to some error handler.

These provide support for self-healing memory, but what about errors in the logic? See DIVA paper and https://caesr.uwaterloo.ca/2013/11/08/urisc-micro/ ("Reliable Computing with Ultra-Reduced Instruction Set Co-processors").